Buffer circuits (e.g., output buffers, input buffers, and bidirectional buffers) are employed in a variety of electronic devices and applications. Certain portable devices, including wireless handsets, notebook computers and personal digital assistants (PDAs), often employ circuitry which runs on two or more different voltage levels. For instance, circuitry utilized with such portable devices may be configured so that a portion of the circuitry, such as, for example, input/output (IO) buffers, runs at a higher power supply voltage level (e.g., about 3.3 volts), as may be supplied by an IO voltage source. Another portion of the circuitry, such as, for example, core logic, may run at a substantially lower power supply voltage level (e.g., about 1.0 volt), as may be supplied by a core voltage source.
There are many applications in which a buffer circuit (e.g., an IO buffer) may be required to operate over a wide range of power supply voltage levels. The level of the power supply voltage source may be determined by the particular application. From a performance standpoint (e.g., speed, power consumption, reliability, etc.), buffer circuits designed to handle a wide range of power supply voltage levels generally do so at the expense of circuit performance. For instance, it is well known that when the power supply voltage level becomes comparable to the core voltage source level, a standard 10 buffer circuit often produces an undesirable amount of skew and operates at a substantially slower speed.
Complementary metal-oxide-semiconductor (CMOS) bidirectional buffers that are required to work over a wide range of power supply voltages often have severe difficulty meeting speed requirements, and/or other requirements, in a low voltage (e.g., about 1.0 volt) range of operation. In an attempt to address this problem, one known approach is to employ a significantly large output buffer stage using transistors suitable for operation at the highest anticipated voltage level. The use of such large transistor sizes, typically several thousand micrometers in width, will cause the buffer size to grow accordingly, often to unacceptable limits, thereby significantly increasing a cost of the buffer circuit. In some applications, several hundred buffers may be required. Moreover, even with these very large sized transistors, a high-frequency operation of the buffers will be rather limited, due primarily to an increased gate capacitance of the large transistor devices.
Accordingly, there exists a need for an improved buffer circuit that does not suffer from one or more of the problems exhibited by conventional buffer circuits.